FIG. 5 shows a cross-section of a recess structure of a prior art FET. In FIG. 5, a undoped GaAs buffer layer 10 is disposed on a semi-insulating GaAs substrate 5. An active layer 4 is disposed on the GaAs buffer layer 10. A recess groove 6 is produced in the active layer 4. Herein, W represents recess width, t represents the recess groove depth, and a represents the thickness of the active layer below the recess groove. A source electrode 1 and a drain electrode 3 are disposed on the active layer 4 at opposite sides of the recess groove, respectively, and a gate electrode 2 is disposed on the surface of the active layer 4 in the recess groove. The active layer 4 provides a current path between the source electrode 1 and the drain electrode 3. The buffer layer 10 reduces the influence of the substrate 5 on the electrical characteristics of the FET.
In an FET, a recess groove is etched to a active layer thickness a in order to obtain a desired channel current. The gate-drain breakdown voltage depends on the gate recess structure in addition to the active layer structure, such as the carrier concentration and the thickness of the active layer. A wider and shallower gate recess structure shows a higher gate-drain breakdown voltage at a given carrier concentration of the active layer and layer thickness beneath the gate electrode. This wider and shallower recess structure, however, causes a large increase in the gate-source resistance (Rs) which has a deleterious effect on the RF characteristics of the FET. In the prior art FET having such a construction, it is difficult to enhance the gate-drain breakdown voltage without a large increase in gate-source resistance only through the optimization of the recess width and recess depth.